1. Technical Field
The present invention generally relates to routing of processor instructions to appropriate execution pipelines in a superscalar processor. More specifically, the present invention relates to reducing complexity of routing of processor instructions to appropriate execution pipelines in a superscalar processor.
2. Description of the Related Art
Instruction level parallelism and superscalar processing can benefit by using an instruction issue queue that can be used dynamically schedule instructions for execution. However, as the number of instructions dispatched to execution units or execution pipelines of a superscalar processor in a clock cycle increases, equations governing routing of which instruction issue queue entry goes to what execution pipeline of the superscalar processor becomes complex. In addition, hazard detection logic must also scan over a greater number of instruction issue queue entries, and this increased scanning can lengthen an amount of time for each clock cycle which can decrease performance of the superscalar processor. These issues are typified in a portion of a conventional super scalar processor illustrated in FIG. 1.
With reference now to FIG. 1, there is depicted a block diagram representation of a portion of a prior art conventional super scalar processor (SSP) 100. Conventional SSP 100 includes an instruction issue queue (IIQ) 110. As shown, IIQ 110 includes IIQ entries 120D0-120D7. Instruction lines 130LN0-130LN7 coupled to and populate respective IIQ entries 120D0-120D7. Populating IIQ 110 starts at IIQ entry 120D0 and continues towards IIQ entry 120D7. Thus, the oldest processor instruction resides in IIQ entry 120D0, a newer processor instruction resides IIQ entry 120D1, and so on. In various designs and/or implementations, an IIQ can include various numbers of IIQ entries.
Conventional SSP 100 includes execution pipelines 140PI, 140PJ, and 140PB coupled to IIQ entries 120D0-120D2. Execution pipeline 140PB executes branch instructions, and execution pipelines 140PI and 140PJ execute non-branch instructions, e.g., integer instructions, floating point instructions, etc. In various designs and/or implementations, a SSP can include various numbers pipelines. As shown, a processor instruction in each of IIQ entries 120D0-120D2 can be routed to each of execution pipelines 140PI, 140PJ, and 140PB, with branch processor instructions routing to execution pipeline 140PB and non-branch processor instructions routing to execution pipelines 140PI and 140PJ.
Since processor instructions residing in IIQ entries 120D0-120D2 are unknown for any clock cycle, there are nine possible routes in routing processor instructions from IIQ entries 120D0-120D2 to execution pipelines 140PI, 140PJ, and 140PB. In some implementations, timing considerations may dictate a late select of three full decoders. For example, an amount of time transpiring for a clock cycle may need to be increased which results in slower processing of processor instructions and, thus, decreased performance. Furthermore, since processor instructions residing in IIQ entries 120D0-120D2 are unknown for any given clock cycle, three possible hazards are to be determined and arbitrated if necessary. A possible hazard can include a read after write (RAW) hazard, a write after write (WAW) hazard, or a write after read (WAR) hazard. For example, a possible hazard to be determined whether or not to exist (and arbitrated if necessary) occurs with IIQ entry 120D2 and IIQ entries 120D1 and 120D0, and a possible hazard to be determined whether or not to exist (and arbitrated if necessary) occurs with IIQ entry 120D1 and IIQ entry 120D0.